FPGA SIGNAL PROCESSING

20+ Projects available.

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  • FPGA SIGNAL PROCESSING
  • Project Code
    Project Title
  • EFFICIENT FPGA-BASED VLSI ARCHITECTURE FOR DETECTING R-PEAKS IN ELECTROCARDIOGRAM SIGNAL BY COMBINING SHANNON ENERGY WITH HILBERT TRANSFORM
  • VLSI DESIGN OF LOW-COST AND HIGH-PRECISION FIXED-POINT RECONFIGURABLE FFT PROCESSORS
  • A UNIVERSAL STRING MATCHING APPROACH TO SCREEN CONTENT CODING
  • A NANO-WATT ECG FEATURE EXTRACTION ENGINE IN 65NM TECHNOLOGY
  • AN ADAPTIVE MECHANISM FOR DESIGNING EFFICIENT SNOOP FILTERS
  • AN EFFICIENT FAULT-TOLERANCE DESIGN FOR INTEGER PARALLEL MATRIX–VECTOR MULTIPLICATIONS
  • MEMORY-BASED ARCHITECTURE FOR MULTICHARACTER AHO–CORASICK STRING MATCHING
  • MODULAR DESIGN OF HIGH-EFFICIENCY HARDWARE MEDIAN FILTER ARCHITECTURE
  • DESIGN AND CHARACTERIZATION OF A LOW-COST FPGA-BASED TDC
  • ENHANCING SENSOR PATTERN NOISE VIA FILTERING DISTORTION REMOVAL FOR HD CAMERA APPLICATIONS
  • A DETERMINISTIC APPROACH TO DETECT MEDIAN FILTERING IN 1D DATA FOR MOTION ESTIMATION ALGORITHM
  • FAST SPECTRUM ANALYSIS FOR AN OFDR USING THE FFT AND SC COMBINATION APPROACH FOR ECG SIGNAL ANALYSIS
  • FLOATING-POINT BUTTERFLY ARCHITECTURE BASED ON BINARY SIGNED-DIGIT REPRESENTATION FOR LOW FIBER OPTICS COMMUNICATION
  • FAULT TOLERANT PARALLEL FFTS ARCHITECTURE USING AN HIGH SPEED PARALLEL ERROR CORRECTION CODES AND PARSEVAL CHECKS
  • A HIGHLY CUSTOMIZABLE LOW-LATENCY COMMUNICATION MAC ARCHITECTURE
  • SOURCE CODING AND PREEMPHASIS FOR DOUBLE-EDGED PULSE WIDTH MODULATION SERIAL COMMUNICATION FOR DOUBLE DYNAMIC RATE BASED WIRELESS COMMUNICATION
  • A REAL-TIME FAULT AWARE NETWORK-ON-CHIP ARCHITECTURE WITH AN EFFICIENT GALS IMPLEMENTATION
  • ASSESSING THE SUITABILITY OF KING TOPOLOGIES FOR INTERCONNECTION NETWORKS
  • A NEW CDMA ENCODING-DECODING METHOD FOR ON-CHIP COMMUNICATION NETWORK
  • ALGORITHM AND ARCHITECTURE OF CONFIGURABLE JOINT DETECTION AND DECODING FOR MIMO WIRELESS COMMUNICATIONS WITH CONVOLUTIONAL CODES
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