High Speed Data Transmission

14+ Projects available.

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  • High Speed Data Transmission
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    Project Title
  • A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

  • An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175 ?W/Channel in 65-nm CMOS

  • Feed forward-Cut set-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

  • An Analog LO Harmonic Suppression Technique for SDR Receivers

  • CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

  • Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI

  • Design of Reconfigurable Digital IF Filter with Low Complexity

  • Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA

  • Analysis and Optimization of Multi section Capacitive DACs for Mixed-Signal Processing

  • A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G

  • A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient

  • An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops

  • Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

  • Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

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