Low power

14+ Projects available.

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    Project Title
  • A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-?m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration

  • Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications

  • Multi loop Control for Fast Transient DC–DC Converter

  • Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation

  • A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC

  • Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs

  • A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-?m CMOS

  • Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

  • Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction

  • Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application

  • A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs

  • Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

  • Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

  • A Wideband Low-Noise Variable-Gain Amplifier with a 3.4 dB NF and up to 45 dB gain tuning range in 130 nm CMOS

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